Dino, Benjamin, Léo from UJF Jospeh Fourier, IUT1, Licence Pro “systemes embarqués”, Grenoble are involved in Xilinx FPGA and SOC University Design contest !!!
Cool! Very nice project and I wish you get a good place! Suggestions for improvements? Describe some use cases where it can be applied. A more evolved example like an oscilliscope could be better. Some photos would make it clearer to non-experts. Why not add a gui e.g. web or mobile gui using mTango. Just some ideas if you have the time.
we registered again a team from the class “Lpro Systèmes embarqués” UJF Grenoble in the Xilinx University Contest, OpenHardware 2016 (http://www.openhw.eu/)
our project is the AmpereHourMeter Tango device server (aka Bouteillometer) revamping… This device is measuring current in TFL (Radiation Dose estimation in Transfer line 1 & 2)
this proof of concept is built with a ZedBoard (Xilinx SoC Zynq 7020), featuring :
Assymetric MultiProcessor : one ARM core for linux/tango device server and use the other one for a standalone bare metal app driving interlock (human safety can’t rely on a non deterministic linux app)
use Zynq internal XADC
Communication between cores use Xilinx On Chip Memory
my class did not win the Xilinx the university contest this year è_é… see result here : http://www.openhw.eu/2016-finalists
but Tango raised some interest in the Valley. I have been invited at Xilinx head quarter in San Jose to the upcoming Xilinx Community Conference October, 5-7… I will emphasize that many of their SoC (zynq and al.) design will perfectly match Tango usage and could be easily combined and reduce TTM etc etc
if you have some message to transmit, feel free to give me some ideas:-)